1. Field of the Invention
The invention generally relates to a method for operating a memory array, and more particularly, to a method for erasing a selected memory cell in a memory array.
2. Description of Related Art
Semiconductor memories can be categorized into volatile memories and non-volatile memories. Data stored in a non-volatile memory (for example, a flash memory) can be retained even when no power is supplied. Flash memory has been developed and applied for high density data storage, such as memory cards in digital cameras, memories in MP3 players, and universal serial bus (USB) memory devices. Besides, flash memory has also been applied as storage devices of personal computers (PCs), such as solid state drive (SSD). Thereby, flash memory is a very promising product in the market of memories.
FIG. 1 is a diagram of a NAND memory array 100. Referring to FIG. 1, the NAND memory array 100 includes a plurality of memory cell strings (for example, memory cell strings 150_1-150_2). Each of the memory cell strings has a select transistor, a plurality of memory cells, and a ground transistor that are connected with each other in series. Each of the memory cell strings is connected to a corresponding word line. The gates of the select transistors and the ground transistors are respectively coupled to a string select line SSL and a ground select line GSL so that the voltages on two ends of the memory cell strings can be applied respectively through the string select line SSL and the ground select line GSL. For example, the memory cell string 150_1 includes a select transistor SW11, memory cells 101-132, and a ground transistor SW12, wherein the memory cells 101-132 are respectively and coupled to word lines WL1-WL32. One ends of the select transistors SW11 and SW21 are respectively and coupled to bit lines BL1 and BL2, and the other ends of the ground transistors SW12 and SW22 are both applied to a ground voltage GND.
Conventionally, the NAND memory array 100 is usually erased in unit of memory block. For example, the memory cell strings 150_1-150_2 are considered a same memory block, the substrates of all the memory cells (for example, the memory cells within the dotted frame 160) in the memory block are applied to a power supply of 20V (i.e., the voltage Vs on the substrates is made to be equal to 20V), and the bit lines BL1-BLN are floated. Next, the gates of the select transistor SW11 and the ground transistor SW12 are applied to the supply voltage Vcc or floated through the string select line SSL and the ground select line GSL, so that both ends of the memory cell strings 150_1-150_2 are floated. After that, a ground voltage GND is supplied to the word lines WL1-WL32 so that a high-voltage drop is produced between the gate and substrate of each memory cell. Accordingly, electrons in the floating gate of each memory cell can pass through the oxide layer of the memory cell and enter the substrate, so that the memory cell is erased. Such an erasing technique is referred to as the Fowler-Nordheim (FN) tunnelling technique.
Generally speaking, existing memory arrays are usually erased through the FN tunneling technique described above. However, because the FN tunnelling technique requires to apply a larger voltage drop (for example, a voltage drop greater than 20V) to produce a large enough vertical electric field, a high operating voltage is needed. In addition, only a limited number of programming-erasing (P/E) cycles can be performed on a flash memory. For example, an industrial flash memory can be programmed-erased for 100,000 times. However, the conventional FN tunnelling technique can only erase a memory array in unit of an entire memory block. Thus, it is impossible to erase a single memory cell through the FN tunnelling technique. In other words, random data reading and writing operations but no random erasing operation can be performed on any selected memory cell in a memory array.
Thereby, how to erase a selected memory cell and, at the same time, reduce the operating voltage has become a major subject regarding the erasing of flash memory.